1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a non-volatile semiconductor memory and a method of operating the same.
2. Discussion of the Related Art
A semiconductor memory device capable of reading and writing digital data electrically is divided into an EEPROM enabling to program and erase data by a cell unit and a flash memory enabling to erase data only by a block unit over several tens and hundreds bytes and record data by a byte unit.
A conventional EEPROM has been widely used to re-write data by using a small data unit. However, the conventional EEPROM cell includes a pair of transistors. Thus, it occupies a relatively large area. As a result, the conventional EEPROM has a difficulty in realizing a large capacity. In addition, it is fabricated with a high cost.
A memory cell of the conventional flash memory including only one transistor increases an erase unit size instead of reducing a cell size. However, the conventional flash memories have some difficulties in achieving desirable operational characteristics and device reliabilities. Such problems become serious as a design rule is reduced, thereby becoming obstacles or limitations for reducing a cell size.
Such non-volatile memories are fabricated by using various processes to be used for a single memory device. In order to build various functional blocks in SoC (system-on-chip) where the various functional blocks forming a system are integrated on one chip, an EEPROM and a flash memory should be fabricated through the same manufacturing process. In addition, each of the cell sizes thereof should be reduced. Further, they should be operable in low supply voltage.
A non-volatile memory according to a related art is explained by referring to the attached drawings as follows.
FIG. 1A illustrates a cross-sectional view of a single transistor type flash memory cell according to the related art, and FIG. 1B illustrates a layout of the single transistor type flash memory cell of FIG. 1A.
Referring to FIG. 1A, the cell includes a source region 2 and a drain region 3 formed in the surface area of a P-type semiconductor substrate 1. A channel region will be generated between the source and drain regions 2 and 3. A gate oxide layer 4, a floating gate 5, and a control gate 7 are stacked on the channel region of the substrate 1. An inter-poly oxide (IPO) layer 6 is formed between the floating and control gates 5 and 7.
The floating gate 5 stores electric charges therein while the control gate 7 induces a voltage on the floating gate 5.
The floating and control gates 5 and 7 are formed as a stacked structure, as shown in FIG. 1A. The source and drain regions 2 and 3 are formed in the semiconductor substrate 1 to be in parallel with both lateral sides of the stacked gates, thereby forming a unit block of a single transistor. A channel hot carrier injection is generally used for a cell programming in this type cell.
Specifically, for the cell programming, about 5V is applied to the drain region 3. The source region 2 is grounded (0V). About 8V is applied to the control gate 7. Thus, hot channel electrons are injected into the floating gate 5.
When an erasing is carried out on the unit block, 0V or a negative high voltage is applied to the control gate 7 while a positive high voltage is applied to the source region 2 or the semiconductor substrate 1. Thus, a tunneling of the electric charges occurs in the direction of the source region 2 or the semiconductor substrate 1.
FIG. 1B illustrates a layout of the flash memory cell having the stacked structure shown in FIG. 1A.
Referring to FIG. 1B, unit cells 11 are separated from each other by a field insulating area 10. Each control gate 15 of the respective cells is connected to a corresponding word line 12. The word lines 12 are separated from each other. A bit line 13 is formed in the direction perpendicular to the word line 12, and each drain region 17 of the respective cells is connected to the bit line 13 through a bit line contact 14.
Although the single transistor stacked type cell has a reduced cell size, it has serious disadvantages as follows. When erasing data in every non-volatile memory, over-erasure phenomena, a threshold voltage of a cell dropped below 0V during erasing, may take place statistically. On a non-volatile memory with a single transistor staked type cell, if at least one cell in a selected bit line is over-erased, it is unable to read the status of the cells in the same bit line.
Generally, non-uniformity in the manufacturing process and process-induced stress applied to a dielectric layer surrounding the floating gate may cause the over-erasure. A designing technique may solve such an over-erasure problem. Meanwhile, a circuit construction becomes complicated. Therefore, the over-erasure in a single transistor staked type cell should be eliminated at all costs.
In addition, the over-erasure is not allowed in the single transistor stacked type cell and furthermore, an erasing is carried out by the block unit over several tens kilobytes, thereby broadening a statistical threshold voltage distribution of the erased block. Therefore, an actual range of the allowable threshold voltage range becomes much narrower.
An electric charge status in the non-volatile memory cell (i.e., the threshold voltage) corresponds to a logical status of the memory cell. A range of the allowable threshold voltage of the single transistor stacked type cell lies approximately between 1V and 5V.
When a reading voltage of 3.3V is applied to the control gate, a cell current proportional to a difference between 3.3V and 1.0V flows in case that a low level of the threshold voltage is 1V. In the cell programmed with 5V, a current fails to flow since a channel of the cell is blocked.
Therefore, it stores digital data of 1 bit in each cell by reading the current conditions in the following and blocking corresponding to two levels of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively.
Meanwhile, a data reading speed of a memory is proportional to the cell current on the reading. Thus, the speed becomes faster when the cell current is large, while the speed becomes slower when the cell current is small. Therefore, the lower the low level of the threshold voltage is, the larger the cell current is and the faster the reading speed is.
The single transistor stacked type cell according to the related art has a relatively high threshold voltage of over 0V in the low level. Thus, it has a small cell current so that it makes very difficult to improve a reading speed without increasing the read voltage applied to the control gate over the supply voltage level. If the threshold voltage of each memory cell is defined as more than four levels, each of the memory cells enables to store logic data having two bits or more (multi-bits memory). When a programming is carried out with multi-levels, four or more levels of the threshold voltage between the allowable threshold voltages of 1V to 5V should be programmed and read.
In this case, when intervals between the threshold voltage levels become narrower, a reading speed becomes slower and the cell is vulnerable to various noises. Therefore, the intervals in the threshold voltage cannot be reduced further. The wide intervals of the entire allowable threshold voltage range enable to readily realize a multi-bits memory as well as increase a memory speed.
Unfortunately, the single transistor stacked type memory cell having a narrow range of the allowable threshold voltage is unable to realize a reading operation with a high speed and a low voltage. Thus, it is difficult to be implemented as a high-speed multi-bits memory.
Further, the single transistor stacked type cell has much difficulty in reducing a size in accordance with a design rule in the scale under about 0.18 xcexcm, thereby causing problems/disadvantages in cell characteristics and reliability.
A drain of a floating gate storage transistor, which corresponds to a cell in a memory array constructed with the above-described cells, is directly connected to a bit line, while a source terminal thereof is connected to a common ground line.
In such a memory array, a drain-turn-on, a punch-through or a high leakage current occurs due to the coupling to the floating gate by a drain voltage. Hence, during the programming, an over-current is produced by the unselected cells on the selected bit line. Such an effect is amplified as the channel length becomes shorter, so that it is difficult to reduce a cell size.
Moreover, in such a memory array, there are problems such as a hot electron injection, which is caused by a leakage current for the unselected cells on the selected bit line, and stored electric charge leakage due to an electric field stress and the like. Such problems become more serious in a multi-bits cell having narrow intervals between the levels of the threshold voltage.
Processes of forming contacts and metal lines are carried out on the drain side of the storage transistor, thereby degrading an oxide layer near the floating gate of the cell during the processes.
Due to all the problems/disadvantages as discussed above, the cell size can be hardly reduced in accordance with the miniaturization of the processes as long as a flash memory cell includes a single transistor.
Unfortunately, the single transistor stacked type cell is improper for incorporating a system chip with a logic process as well as a stand-alone non-volatile memory for a deep sub-micron process technology.
Generally, the stacked type cell as shown in FIGS. 1A and 1B having a low coupling ratio for a control gate is disadvantageous in a low voltage operation. An increased coupling ratio of a non-volatile memory cell is absolutely necessary for efficiently coping with a system driven by a lower voltage such as portable devices.
The problems/disadvantages of the single transistor stacked type cell may be overcome by adding a serially connected floating gate transistor (I) and a selection transistor (II) as a two-transistor EEPROM cell, in FIG. 2A.
FIG. 2A illustrates a cross-sectional view of a two-transistor EEPROM cell according to a related art, and FIG. 2B illustrates a layout of the two-transistor EEPROM cell in FIG. 2A. FIGS. 2C and 2D illustrate circuits of two-transistor EEPROM cells according to related arts.
Referring to FIG. 2A, the two-transistor EEPROM cell includes source and drain regions 22 and 23 formed in the surface area of a P-type semiconductor substrate 21. A portion between the source and drain regions 22 and 23 becomes a channel region. A gate oxide layer 24 and a floating gate 25 are formed on the channel region. A control gate 27 surrounds the floating gate 25.
A dielectric (inter-poly oxide) layer 26 is formed between the floating gate 25 and the control gate 27.
The floating gate 25 stores electric charges, and the control gate 27 induces a voltage on the floating gate 25.
A selection transistor (II) uses the drain region 23 of a floating gate transistor (I) as a source region thereof. The selection transistor has another drain region 23a leaving another channel region therebetween, and is formed at one side of the floating gate transistor (I).
On the channel region of the selection transistor (II), another gate oxide layer 24a having a thickness equal to or different from the gate oxide layer of the floating gate oxide layer 24. A gate 28 of the selection transistor (II) is formed on the gate oxide layer 24a. 
A layout of the above-described cell is shown in FIG. 2B. In the EEPROM according to the related art, control gates of adjacent cells on the same active region should be separated from each other with a margin xe2x80x98Bxe2x80x99 by photolithography and an etch process as follows.
As well known in the art, a minimum size of a circuit line width is limited by a resolution of photolithography.
The EEPROM shown in FIGS. 2A and 2B has a floating gate and a control gate defined over the floating gate by lithography. It requires a margin xe2x80x98Axe2x80x99 amounting to a process tolerance at the side of the floating gate. Therefore, the EEPROM according to the related art is inevitably increased in its cell size as long as the margin xe2x80x98Axe2x80x99 and xe2x80x98Bxe2x80x99 exist in FIGS. 2A and 2B.
Further, in the EEPROM according to the related art, a high voltage greater than 15V is applied to a source or drain junction of the cell. Thus, it has large-sized p-n junction of the respective terminals, thereby increasing the cell size.
Arrays of the EEPROM according to the related art are illustrated as shown in FIGS. 2C and 2D. In FIG. 2C, a drain of a selection transistor is connected to a bit line. On the other hand, a drain of a storage transistor (floating gate transistor) is connected to a bit line in FIG. 2D.
In these array architectures, each control gate line is separated at every row and a control gate of each cell at the row is connected to the control gate line of the corresponding row.
Thus, the array composed of the control gate lines separated on every row requires complicated circuitry in decoding the respective lines.
Accordingly, the present invention is directed to a non-volatile semiconductor memory and a method of operating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide the non-volatile semiconductor memory and the method of operating the same that enables to maintain a stable operation and provides reliability.
Another object of the present invention is to provide the non-volatile semiconductor memory and the method of operating the same that enables to realize a small cell size and reduces a cell size in accordance with a down-scale in photolithography.
A further object of the present invention is to provide the non-volatile semiconductor memory and the method of operating the same that realizes a high-speed multi-bits operation.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a non-volatile semiconductor memory according to the present invention includes a semiconductor substrate having active and field regions, at least two non-volatile storage transistors each having a storage at the active region and a control gate at the storage, wherein each control gate is incorporated into a single control plate, and at least two select transistors each of which corresponds to each non-volatile storage transistor, wherein each of the selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistors.
Accordingly, the present invention reduces a cell size greatly and simplifies its fabrication process by incorporating a plurality of control gates of the at least two adjacent cells into a single body in a two-transistor structure.
The present invention provides many advantages such as operational stability and device reliance of a two-transistor structure as well as a feasibility of a high-speed multi-bits non-volatile memory in a low-voltage.
In the present invention, each non-volatile memory cell includes at least one selection transistor.
The control plate is unable to be realized by a single transistor cell because a control gate in the single transistor cell works as a selection transistor to select a cell. Namely, if the control gate connects two adjacent cells, adjacent word lines are short-circuited to each other in an array. Thus, it is unable to select one of the word lines independently.
In the present invention, the selection gate is separated from the control plate. Thus, the control gates of the two adjacent cells are connected to each other through one body. Namely, even if the non-volatile storage transistors of the cells located on at least two rows (word lines) and the same bit line (column), a selectivity of the respective cells, which is governed by each of the corresponding selection transistors, is free from such an influence.
Accordingly, in a non-volatile memory cell according to the present invention, at least one selection transistor corresponding to a non-volatile storage transistor in each cell is connected in series to one end or both ends of the non-volatile storage transistor. Moreover, the non-volatile storage transistor may be separated from the selection transistor through a junction as a source or drain. Instead, the non-volatile storage and selection transistors may have a split-gated structure in which gates are split from each other on one continuous channel. Further, the control plate of the non-volatile semiconductor memory according to the present invention may cover two adjacent cells or a block unit comprising at least two adjacent cells.
In another aspect of the present invention, in a non-volatile semiconductor memory including at least two non-volatile storage transistors each of which including a source in the substrate, a drain in the substrate, a storage on the dielectric layer over the active region, and a control gate at the storage, at least two control gates incorporating into a control plate built in a single body, and at least two selection transistors each of which including a source in the substrate, a drain in the substrate, a selection gate on the dielectric layer between the source and the drain to be isolated from the storage, wherein the source of each of the selection transistors is the drain of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor, a method of operating the non-volatile semiconductor memory includes selecting one of the non-volatile storage transistors by turning on or off the respective selection transistors, and programming the selected non-volatile storage transistor using a hot carrier injection method generating hot electrons from a channel of the selected non-volatile storage transistor.
Preferably, the channel hot carrier injection method is one of a first method of applying a reverse bias having a predetermined level between the source of the selected non-volatile storage transistor and the substrate, a second method of increasing a voltage of the control plate of the selected non-volatile storage transistor gradually from a low voltage, and a third method of combining the first and second methods.
Preferably, the stored electric charges are discharged for an erasing operation by forming a high electric field between the storage of the corresponding non-volatile storage transistor and the source or substrate using tunneling.
Preferably, for a reading operation, the selection transistor of the selected cell is turned on and a proper positive voltage is applied thereto in accordance with a read current required for the control plate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.